( en | de | ru )

 

Disambiguation of "Alizadeh, Bijan"

Author of the publication

copydeleteadd this publication to your clipboard
Systematic Trojan Detection in Crypto-Systems Using the Model Checker.

, , and . J. Circuits Syst. Comput., (February 2024)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jasmin Bijani

Khosrow Alizadeh

Alireza Alizadeh

Hüssein Alizadeh

Mansour Alizadeh

 

Other publications of authors with the same name

Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA., , , , , , and . FPT, page 370-373. IEEE, (2014)Modular arithmetic decision procedure with auto-correction mechanism., and . HLDVT, page 138-145. IEEE Computer Society, (2009)A formal approach to debug polynomial datapath designs.. ASP-DAC, page 683-688. IEEE, (2012)Data-path aware high-level ECO synthesis., , and . Integr., (2019)Low power scheduling in high-level synthesis using dual-Vth library., , and . ISQED, page 507-511. IEEE, (2015)Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams., , , , , , and . ISCAS (1), page 424-427. IEEE, (2005)Debugging and optimizing high performance superscalar out-of-order processors using formal verification techniques., and . ISQED, page 297-302. IEEE, (2011)Systematic approximate logic optimization using don't care conditions., , , and . ISQED, page 419-425. IEEE, (2017)UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications., , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (10): 994-998 (2016)Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits., and . IEEE Trans. Circuits Syst., 67-II (12): 3063-3067 (2020)