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A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration.

, , , , , and . DATE, page 1336-1341. IEEE, (2017)

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Timing Driven Placement for Large Standard Cell Circuits., and . DAC, page 211-215. ACM Press, (1995)Efficient timing closure without timing driven placement and routing., , , and . DAC, page 268-273. ACM, (2004)Issues in global routing.. ISPD, page 142-147. ACM, (2008)Analysis of post-placement length estimation., , , and . SLIP, page 23. ACM, (2012)Design Obfuscation through Selective Post-Fabrication Transistor-Level Programming., , , , , , , and . DATE, page 528-533. IEEE, (2019)A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration., , , , , and . DATE, page 1336-1341. IEEE, (2017)A Detailed Routing-Aware Detailed Placement Technique., , , , , and . ISVLSI, page 38-43. IEEE Computer Society, (2015)Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA., , , , , , , and . ACM Great Lakes Symposium on VLSI, page 171-176. ACM, (2019)Toward an Open-Source Digital Flow: First Learnings from the OpenROAD Project., , , , , , , , , and 11 other author(s). DAC, page 76. ACM, (2019)A new generalized row-based global router., and . ICCAD, page 491-498. IEEE Computer Society / ACM, (1993)