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Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection.

, , , , и . DATE, стр. 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)

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Marc Bonhomme

Stéphane Bonhomme

Oriane Bonhomme

Yannick Antoniazza

Yannick Zakowski

 

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Programmable extended SEC-DED codes for memory errors., , , и . VTS, стр. 140-145. IEEE Computer Society, (2011)Power-Driven Routing-Constrained Scan Chain Design., , , , и . J. Electron. Test., 20 (6): 647-660 (2004)Memory Reliability Improvement Based on Maximized Error-Correcting Codes., , и . J. Electron. Test., 29 (4): 601-608 (2013)Memory reliability improvements based on maximized error-correcting codes., , и . European Test Symposium, стр. 1-6. IEEE Computer Society, (2012)Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection., , , , и . DATE, стр. 1077-1082. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Programmable restricted SEC codes to mask permanent faults in semiconductor memories., , и . IOLTS, стр. 147-153. IEEE Computer Society, (2010)An efficient scan tree design for test time reduction., , , и . ETS, стр. 174-179. IEEE Computer Society, (2004)Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint., , , , и . ITC, стр. 488-493. IEEE Computer Society, (2003)Power Driven Chaining of Flip-Flops in Scan Architectures., , , и . ITC, стр. 796-803. IEEE Computer Society, (2002)Generalized parity-check matrices for SEC-DED codes with fixed parity., , , и . IOLTS, стр. 198-201. IEEE Computer Society, (2011)