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Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost.

, , , , и . IPSJ Trans. Syst. LSI Des. Methodol., (2017)

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Toshinori Kuwahara

 

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An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture., , , , и . Int. J. Reconfigurable Comput., (2008)The Kyushu University reconfigurable parallel processor: design of memory and intercommunicaiton architectures., , , , и . ICS, стр. 351-360. ACM, (1989)A 3D FPGA Architecture to Realize Simple Die Stacking., , , , и . IPSJ Trans. Syst. LSI Des. Methodol., (2015)Basic Knowledge to Understand FPGAs.. Principles and Structures of FPGAs, Springer, (2018)A novel FPGA design framework with VLSI post-routing performance analysis (abstract only)., , , , , и . FPGA, стр. 271. ACM, (2013)A novel states recovery technique for the TMR softcore processor., , , , , и . FPL, стр. 543-546. IEEE, (2009)Improving the Soft-error Tolerability of a Soft-core Processor on., , , , и . J. Next Gener. Inf. Technol., 2 (3): 35-48 (2011)Evaluation of fault tolerant technique based on homogeneous FPGA architecture., , , , , и . VLSI-SoC, стр. 225-230. IEEE, (2012)KITE microprocessor and CAE for computer science., , и . Syst. Comput. Jpn., 33 (8): 64-74 (2002)DoS/DDoS Detection Scheme Using Statistical Method Based on the Destination Port Number., , , и . IIH-MSP, стр. 206-209. IEEE Computer Society, (2009)