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Disambiguation of "Mathew, Sanu K."

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Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks.

, , , , , , , , and . CICC, page 1-2. IEEE, (2021)

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Muhammad Sanusi

Stanley Mathew

Rebecca Mathew

Mathew Joseph

Mathew George

 

Other publications of authors with the same name

A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 40 (1): 44-51 (2005)An 8.3-to-18Gbps Reconfigurable SCA-Resistant/Dual-Core/Blind-Bulk AES Engine in Intel 4 CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2022)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks., , , , , , , , and . CICC, page 1-2. IEEE, (2021)A Time-/Frequency-Domain Side-Channel Attack Resistant AES-128 and RSA-4K Crypto-Processor in 14-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (4): 1141-1151 (2021)An All-Digital Unified Physically Unclonable Function and True Random Number Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction in 14-nm Tri-gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (4): 1074-1085 (2019)Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC)., , , , and . IEEE J. Solid State Circuits, 58 (1): 3-7 (2023)A 9-GHz 65-nm Intel® Pentium 4 Processor Integer Execution Unit., , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 26-37 (2007)A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS., , , , , , and . IEEE J. Solid State Circuits, 44 (1): 107-114 (2009)