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A mixed-mode ESD protection circuit simulation-design methodology., , , , , , , and . IEEE J. Solid State Circuits, 38 (6): 995-1006 (2003)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism., , , and . ISCAS (5), page 217-220. IEEE, (2004)ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress., , , and . ASP-DAC, page 79-82. ACM Press, (2005)ESDInspector: a new layout-level ESD protection circuitry design verification tool using a smart-parametric checking mechanism., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (10): 1421-1428 (2004)Bonding-pad-oriented on-chip ESD protection structures for ICs., , , , , , and . ISCAS (1), page 741-744. IEEE, (2003)A 3D mixed-mode ESD protection circuit simulation-design methodology., , , , , and . CICC, page 243-246. IEEE, (2004)A 5 GHz sub-harmonic direct down-conversion mixer for dual-band system in 0.35µm SiGe BiCMOS., , , , , and . ISCAS (5), page 4807-4810. IEEE, (2005)ESDExtractor: A new technology-independent CAD tool for arbitrary ESD protection device extraction., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (10): 1362-1370 (2003)ESD protection design for RF integrated circuits: new challenges., , , , and . CICC, page 411-418. IEEE, (2002)Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verification., , , , , , and . ASP-DAC, page 710-712. IEEE Computer Society, (2004)