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A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.

G. Matsukawa, T. Kodama, Y. Nishizumi, K. Kajihara, C. Nakanishi, S. Izumi, H. Kawaguchi, T. Goto, T. Kato, and M. Yoshimoto. IEICE Electron. Express, 14 (15): 20170668 (2017)

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GO

Minoru Matsukawa

Kohan Go

Bansing Go

Li-mei Go

Other publications of authors with the same name

Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.G. Matsukawa, Y. Kimi, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations.R. Kawamoto, M. Taichi, M. Kabuto, D. Watanabe, S. Izumi, M. Yoshimoto, H. Kawaguchi, G. Matsukawa, T. Goto, and M. Kojima. IEEE J. Sel. Top. Signal Process., 14 (4): 634-645 (2020)Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path.Y. Kimi, G. Matsukawa, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. ATS, page 139-144. IEEE Computer Society, (2015)FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature.Y. Nishizumi, G. Matsukawa, K. Kajihara, T. Kodama, S. Izumi, H. Kawaguchi, C. Nakanishi, T. Goto, T. Kato, and M. Yoshimoto. SiPS, page 1-6. IEEE, (2017)An soft error propagation analysis considering logical masking effect on re-convergent path.S. Yoshida, G. Matsukawa, S. Izumi, H. Kawaguchi, and M. Yoshimoto. IOLTS, page 13-16. IEEE, (2016)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme.G. Matsukawa, Y. Nakata, Y. Sugure, S. Oho, Y. Kimi, M. Shimozawa, S. Yoshida, H. Kawaguchi, and M. Yoshimoto. IEICE Trans. Electron., 98-C (4): 333-339 (2015)A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.G. Matsukawa, T. Kodama, Y. Nishizumi, K. Kajihara, C. Nakanishi, S. Izumi, H. Kawaguchi, T. Goto, T. Kato, and M. Yoshimoto. IEICE Electron. Express, 14 (15): 20170668 (2017)A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668.G. Matsukawa, T. Kodama, Y. Nishizumi, K. Kajihara, C. Nakanishi, S. Izumi, H. Kawaguchi, T. Goto, T. Kato, and M. Yoshimoto. IEICE Electron. Express, 15 (12): 20188003 (2018)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM.G. Matsukawa, Y. Nakata, Y. Kimi, Y. Sugure, M. Shimozawa, S. Oho, H. Kawaguchi, and M. Yoshimoto. ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)An accurate soft error propagation analysis technique considering temporal masking disablement.Y. Kimi, G. Matsukawa, S. Yoshida, S. Izumi, H. Kawaguchi, and M. Yoshimoto. IOLTS, page 23-25. IEEE, (2015)

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Disambiguation of "Matsukawa, Go"

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A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.

Please choose a person to relate this publication to

GO

Minoru Matsukawa

Kohan Go

Bansing Go

Li-mei Go

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Matsukawa, Go"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.

Please choose a person to relate this publication to

GO

Minoru Matsukawa

Kohan Go

Bansing Go

Li-mei Go

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video.