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Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path.

, , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)

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Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 99-A (6): 1198-1205 (2016)A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement., , , , , , , , , and 4 other author(s). ISQED, page 16-23. IEEE, (2014)Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path., , , , , and . ATS, page 139-144. IEEE Computer Society, (2015)A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme., , , , , , , , and . IEICE Trans. Electron., 98-C (4): 333-339 (2015)A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation., , , , , , , , , and 4 other author(s). IEICE Trans. Electron., 97-C (4): 332-341 (2014)An accurate soft error propagation analysis technique considering temporal masking disablement., , , , , and . IOLTS, page 23-25. IEEE, (2015)A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM., , , , , , , and . ARCS Workshops, page 1-5. VDE Verlag / IEEE Xplore, (2014)