( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging.

, , , , , и . IPDPS, стр. 254-264. IEEE Computer Society, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Arno Kahne

Arno Kahne

Rolf-Walter Briant

Benoît Briand

Rudolf Kähne

 

Другие публикации лиц с тем же именем

MINIME-validator: Validating hardware with synthetic parallel testcases., , и . DATE, стр. 386-391. IEEE, (2017)MINIME: Pattern-Aware Multicore Benchmark Synthesizer., , , и . IEEE Trans. Computers, 64 (8): 2239-2252 (2015)Accelerating Synchronization Using Moving Compute to Data Model at 1, 000-core Multicore Scale., , , и . ACM Trans. Archit. Code Optim., 16 (1): 4:1-4:27 (2019)Functional Validation of a New Network Switch Architecture Using Rapid Prototyping Techniques., и . MTV, стр. 3-7. IEEE Computer Society, (2013)Using software architectural patterns for synthetic embedded multicore benchmark development., , , и . IISWC, стр. 89-99. IEEE Computer Society, (2012)Stream synthesis for a wormhole run-time reconfigurable platform., и . FPL, том 1304 из Lecture Notes in Computer Science, стр. 101-110. Springer, (1997)MBET: Resilience Improvement Method for DNNs., , , и . AITest, стр. 72-78. IEEE, (2022)Retiming Verification Using Sequential Equivalence Checking., и . MTV, стр. 138-142. IEEE Computer Society, (2005)Accelerating Graph and Machine Learning Workloads Using a Shared Memory Multicore Architecture with Auxiliary Support for In-hardware Explicit Messaging., , , , , и . IPDPS, стр. 254-264. IEEE Computer Society, (2017)Multicore Resource Isolation for Deterministic, Resilient and Secure Concurrent Execution of Safety-Critical Applications., , , и . IEEE Comput. Archit. Lett., 17 (2): 230-234 (2018)