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Disambiguation of "Hamashita, Koichi"

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Adaptive cancellation of gain and nonlinearity errors in pipelined ADCs.

, , , , , and . ISSCC, page 282-283. IEEE, (2013)

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Koichi Matsumoto

Koichi Koshi

Koichi Morikawa

 

Other publications of authors with the same name

A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator., , , , and . CICC, page 9-12. IEEE, (2009)A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays., , , , , , , and . ESSCIRC, page 221-224. IEEE, (2015)A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry., , , and . A-SSCC, page 1-2. IEEE, (2020)A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR., , , , , , and . ISSCC, page 494-495. IEEE, (2008)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)Binary Access Memory: An optimized lookup table for successive approximation applications., , , , and . ISCAS, page 1620-1623. IEEE, (2011)A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers., , , , , and . A-SSCC, page 325-328. IEEE, (2016)A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier., , , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3410-3420 (2019)A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application., , , , , , and . CICC, page 1-4. IEEE, (2011)A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW., , , , , and . CICC, page 1-4. IEEE, (2017)