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Disambiguation of "Asada, Kunihiro"

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Yield-Optimal Layout Synthesis of CMOS Logic Cells by Wiring Fault Minimization.

, , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 88-A (7): 1957-1963 (2005)

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Kunihiro Jojima

 

Other publications of authors with the same name

Extension of power supply impedance emulation method on ATE for multiple power domain., , , , , , and . ETS, page 1-2. IEEE, (2017)High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design., , , , , and . ASP-DAC, page 255-260. IEEE, (2013)On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure., , , , , and . ESSCIRC, page 183-186. IEEE, (2011)A Pulse Width controlled PLL and its automated design flow., , , and . ICECS, page 5-8. IEEE, (2013)Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology., , , , and . ICECS, page 220-223. IEEE, (2011)An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator., , , and . CICC, page 1-4. IEEE, (2013)A general and efficient mask pattern generator for non-series-parallel CMOS transistor network., and . Synthesis for Control Dominated Circuits, volume A-22 of IFIP Transactions, page 323-333. North-Holland, (1992)A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer., , , and . ISCAS, page 93-96. IEEE, (2014)Range extension of inductive coupling communication using multi-stage resonance., , and . ISCIT, page 758-763. IEEE, (2012)Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board., , , , , , and . ITC, page 1-8. IEEE, (2016)