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A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.

D. Jacquet, F. Hasbani, P. Flatresse, R. Wilson, F. Arnaud, G. Cesana, T. Gilio, C. Lecocq, T. Roy, A. Chhabra, C. Grover, O. Minez, J. Uginet, G. Durieu, C. Adobati, D. Casalotto, F. Nyer, P. Menut, A. Cathelin, I. Vongsavady, and P. Magarshack. IEEE J. Solid State Circuits, 49 (4): 812-826 (2014)

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Philippe Destouches

Philippe Staib

Philippe Kersting

Philippe Bopp

Philippe Dreuw

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UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency.P. Magarshack, P. Flatresse, and G. Cesana. DATE, page 952-957. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.P. Flatresse, B. Giraud, J. Noel, B. Pelloux-Prayer, F. Giner, D. Arora, F. Arnaud, N. Planes, J. Coz, O. Thomas and 4 other author(s). ISSCC, page 424-425. IEEE, (2013)Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs.P. Flatresse. ISLPED, page 127-130. ACM, (2014)Bottom-up digital system-level reliability modeling.N. Amador, V. Huard, E. Pion, F. Cacho, D. Croain, V. Robert, S. Engels, P. Flatresse, and L. Anghel. CICC, page 1-4. IEEE, (2011)A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors.D. Rossi, I. Loi, A. Pullini, T. Müller, A. Burg, F. Conti, L. Benini, and P. Flatresse. IEEE Des. Test, 34 (6): 46-53 (2017)Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters.A. Bonetti, A. Teman, P. Flatresse, and A. Burg. IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2388-2400 (2017)Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec.J. Coz, P. Flatresse, S. Engels, A. Valentian, M. Belleville, C. Raynaud, D. Croain, and P. Urard. ISSCC, page 336-337. IEEE, (2011)Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.B. Pelloux-Prayer, A. Valentian, B. Giraud, Y. Thonnart, J. Noel, P. Flatresse, and E. Beigné. VLSI-SoC, page 168-173. IEEE, (2013)Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI.K. Akyel, L. Ciampolini, O. Thomas, B. Pelloux-Prayer, S. Kumar, P. Flatresse, C. Lecocq, and G. Ghibaudo. ISCAS, page 1452-1455. IEEE, (2013)A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS.A. Grover, G. Visweswaran, C. Parthasarathy, M. Daud, D. Turgis, B. Giraud, J. Noel, I. Panades, G. Moritz, E. Beigné and 3 other author(s). IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2438-2447 (2017)

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Disambiguation of "Flatresse, Philippe"

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A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.

Please choose a person to relate this publication to

Philippe Destouches

Philippe Staib

Philippe Kersting

Philippe Bopp

Philippe Dreuw

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Flatresse, Philippe"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.

Please choose a person to relate this publication to

Philippe Destouches

Philippe Staib

Philippe Kersting

Philippe Bopp

Philippe Dreuw

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.