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A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications.

, , , , , , , , , и . ISSCC, стр. 222-223. IEEE, (2012)

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Takashi Seki

Takashi Iwata

Takashi Tsuno

Takashi Numaguchi

Takashi Ohtsuki

 

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A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology., , , , , , , , , и 12 other автор(ы). ISSCC, стр. 262-263. IEEE, (2008)Development of Image Recognition Processor Based on Configurable Processor., , , , , , , , и . J. Robotics Mechatronics, 17 (4): 437-446 (2005)Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture., , , , , , , , и . ICCD, стр. 2-7. IEEE Computer Society, (2002)A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications., , , , , , , , , и . VLSIC, стр. 150-151. IEEE, (2012)Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters., , , , , , , , , и . IEICE Trans. Electron., 97-C (4): 360-368 (2014)A 464GOPS 620GOPS/W heterogeneous multi-core SoC for image-recognition applications., , , , , , , , , и . ISSCC, стр. 222-223. IEEE, (2012)A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 326-327. IEEE, (2010)A single-chip MPEG-2 codec based on customizable media embedded processor., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 38 (3): 530-540 (2003)An evaluation of an energy efficient many-core SoC with parallelized face detection., , , , и . ASP-DAC, стр. 311-316. IEEE, (2014)A near-future prediction method for low power consumption on a many-core processor., , , , , , , , , и 2 other автор(ы). DATE, стр. 1058-1059. EDA Consortium San Jose, CA, USA / ACM DL, (2013)