( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Adaptive high-speed and ultra-low power optical interconnect for data center communications.

, , , , , , , и . ICTON, стр. 1-4. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Alessandro Valeri

Fluorescence resonance energy transfer between multiple chromophores studied by single-molecule spectroscopy. Uni Düsseldorf, (2009)

Alessandro Nova

Alessandro Zivelonghi

Alessandro Mirizzi

Alessandro Topa

 

Другие публикации лиц с тем же именем

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 52 (12): 3458-3473 (2017)A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 53 (4): 1227-1237 (2018)Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors., , , и . Microelectron. J., (2016)Background calibration using noisy reference ADC for a 12 b 600 MS/s 2 × TI SAR ADC in 14nm CMOS FinFET., , , , , , , , , и 2 other автор(ы). ESSCIRC, стр. 183-186. IEEE, (2017)A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET., , , , , , , , , и 5 other автор(ы). ISSCC, стр. 476-478. IEEE, (2019)Design space exploration for field programmable compressor trees., , , , , , и . CASES, стр. 207-216. ACM, (2008)3D serial TSV link for low-power chip-to-chip communication., , , и . ICICDT, стр. 1-4. IEEE, (2014)Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs., , , , и . Microelectron. J., (2016)A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 53 (11): 3268-3279 (2018)10.6 continuous-time linear equalization with programmable active-peaking transistor arrays in a 14nm FinFET 2mW/Gb/s 16Gb/s 2-Tap speculative DFE receiver., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)