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A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET.

, , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 29-42 (2019)

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A 112 Gb/s PAM-4 56 Gb/s NRZ Reconfigurable Transmitter With Three-Tap FFE in 10-nm FinFET., , , , , , , , , and . IEEE J. Solid State Circuits, 54 (1): 29-42 (2019)A multiplexer-based digital passive linear counter (PLINCO)., , , and . ICECS, page 607-610. IEEE, (2009)The effect of correlated level shifting on noise performance in switched capacitor circuits., , , and . ISCAS, page 942-945. IEEE, (2012)A 30% beyond VDD signal swing 9-ENOB pipelined ADC using a 1.2V 30dB loop-gain opamp., , , , and . A-SSCC, page 345-348. IEEE, (2011)Binary Access Memory: An optimized lookup table for successive approximation applications., , , , and . ISCAS, page 1620-1623. IEEE, (2011)Design Considerations for Stochastic Analog-to-Digital Conversion., , , and . ICECS, page 234-237. IEEE, (2007)A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers., , , , , and . VLSIC, page 32-33. IEEE, (2012)10.5 A 5.9pJ/b 10Gb/s serial link with unequalized MM-CDR in 14nm tri-gate CMOS., , , , , , , , , and . ISSCC, page 1-3. IEEE, (2015)Design of a Split-CLS Pipelined ADC With Full Signal Swing Using an Accurate But Fractional Signal Swing Opamp., , and . IEEE J. Solid State Circuits, 45 (12): 2623-2633 (2010)Digitally Synthesized Stochastic Flash ADC Using Only Standard Digital Cells., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (1): 84-91 (2014)