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Disambiguation of "Tamura, Hirotaka"

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22.8 A 24-to-35Gb/s x4 VCSEL driver IC with multi-rate referenceless CDR in 0.13um SiGe BiCMOS.

, , , , , , , and . ISSCC, page 1-3. IEEE, (2015)

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Claudia Tamura

Ichiro Tamura

Hitoshi Tamura

Hirotaka Wakatsuki

Hirotaka Yoshida

 

Other publications of authors with the same name

A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS., , , and . ISSCC, page 436-438. IEEE, (2011)A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS., , , , , , , , and . VLSIC, page 1-2. IEEE, (2014)3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS., , , , , , , , , and 7 other author(s). ISSCC, page 64-65. IEEE, (2016)32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 36-37. IEEE, (2013)32Gb/s 28nm CMOS time-interleaved transmitter compatible with NRZ receiver with DFE., , , , , , , , and . ISSCC, page 40-41. IEEE, (2013)6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS., , , , , , and . ISSCC, page 120-121. IEEE, (2017)6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance., , , , and . ISSCC, page 122-123. IEEE, (2017)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)Design metrics for blind ADC-based wireline receivers., and . CICC, page 1-8. IEEE, (2013)Digital Annealer for High-Speed Solving of Combinatorial optimization Problems and Its Applications., , , , , , and . ASP-DAC, page 667-672. IEEE, (2020)