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A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.

R. Ammendola, A. Biagioni, O. Frezza, W. Geurts, G. Goossens, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Ottorino Mazzetta

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Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster.P. Paolucci, R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, E. Pastorelli, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)Design and implementation of a modular, low latency, fault-aware, FPGA-based network interface.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. ReConFig, page 1-6. IEEE, (2013)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.R. Ammendola, A. Biagioni, O. Frezza, W. Geurts, G. Goossens, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula and 2 other author(s). Future Gener. Comput. Syst., (2015)Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.G. Agosta, M. Aldinucci, C. Álvarez, R. Ammendola, Y. Arfat, O. Beaumont, M. Bernaschi, A. Biagioni, T. Boccali, B. Bramas and 46 other author(s). Microprocess. Microsystems, (November 2022)A hierarchical watchdog mechanism for systemic fault awareness on distributed systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, A. Lonardo, P. Paolucci, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. Future Gener. Comput. Syst., (2015)Architectural improvements and technological enhancements for the APEnet+ interconnect system.R. Ammendola, A. Biagioni, O. Frezza, A. Lonardo, F. Cicero, M. Martinelli, P. Paolucci, E. Pastorelli, D. Rossetti, F. Simula and 2 other author(s). CoRR, (2022)Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms.P. Paolucci, A. Biagioni, L. Murillo, F. Rousseau, L. Schor, L. Tosoratto, I. Bacivarov, R. Bücs, C. Deschamps, A. Antably and 11 other author(s). J. Syst. Archit., (2016)TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale.G. Agosta, D. Cattaneo, W. Fornaciari, A. Galimberti, G. Massari, F. Reghenzani, F. Terraneo, D. Zoni, C. Brandolese, M. Celino and 41 other author(s). DSD, page 286-294. IEEE, (2021)The Next Generation of Exascale-Class Systems: The ExaNeSt Project.R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, F. Simula and 8 other author(s). DSD, page 510-515. IEEE Computer Society, (2017)Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems.R. Ammendola, A. Biagioni, O. Frezza, F. Cicero, P. Paolucci, A. Lonardo, D. Rossetti, F. Simula, L. Tosoratto, and P. Vicini. CoRR, (2013)

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Ottorino Mazzetta

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