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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons., , , , , , , , , и 1 other автор(ы). CICC, стр. 1-4. IEEE, (2011)A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration., , , , , , , , и . CICC, стр. 1-4. IEEE, (2015)A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation., , , , , , , , , и . FPGA, стр. 153-162. ACM, (2012)A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS., , , , , , , и . ISSCC, стр. 368-369. IEEE, (2009)3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 56-57. IEEE, (2016)A High-Resolution Minimicroscope System for Wireless Real-Time Monitoring., , , , , , и . IEEE Trans. Biomed. Eng., 65 (7): 1524-1531 (2018)Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion., , , , , , , , , и 4 other автор(ы). CICC, стр. 1-4. IEEE, (2013)22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks., , , , , , , , , и 1 other автор(ы). ISSCC, стр. 1-3. IEEE, (2015)Designing a Testable System on a Chip., , , , , , , , , и 5 other автор(ы). VTS, стр. 2-7. IEEE Computer Society, (1998)A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI., , , , , , , , и . CICC, стр. 1-4. IEEE, (2013)