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Disambiguation of "Yasufuku, Tadashi"

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Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.

, , , , and . IEICE Trans. Electron., 94-C (6): 1072-1075 (2011)

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Tadashi Obara

Tadashi Otsuru

Tadashi Makabe

Tadashi Kito

Tadashi Yamagata

 

Other publications of authors with the same name

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates., , , , , , and . DAC, page 984-989. ACM, (2011)Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 1175-1179 (2013)Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories., , , , , , and . IEICE Trans. Electron., 93-C (3): 317-323 (2010)Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories., , , , , , and . 3DIC, page 1-4. IEEE, (2009)12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains., , , , , and . ESSCIRC, page 191-194. IEEE, (2011)A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS., , , , , , , , , and . ISSCC, page 472-473. IEEE, (2009)Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection., , , , , , , , , and . IEEE J. Solid State Circuits, 45 (1): 249-259 (2010)A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology., , , , , , , , , and 54 other author(s). ISSCC, page 336-338. IEEE, (2018)24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits., , , , , , , , , and 2 other author(s). ISQED, page 586-591. IEEE, (2012)13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO., , , , , , , and . ISSCC, page 486-488. IEEE, (2012)