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Disambiguation of "Murugesan, Mariappan"

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Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory.

, , , , , , , and . 3DIC, page 1-4. IEEE, (2013)

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Kalaimathi Murugesan

Aruljothi Mariappan

Mariappan Sakthivel

Malaiyalam Mariappan

Manju Shrii Murugesan

 

Other publications of authors with the same name

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress., , , , , and . 3DIC, page 1-4. IEEE, (2011)Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI., , , , , , , and . 3DIC, page 1-4. IEEE, (2014)Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing., , , , , , , , , and . 3DIC, page 1-4. IEEE, (2021)Mitigating thermo mechanical stress in high-density 3D-LSI through dielectric liners in Cu- through silicon Via _ µ-RS and µ-XRD study., , , , , , and . 3DIC, page TS8.10.1-TS8.10.5. IEEE, (2015)Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding., , , , , , , , , and 2 other author(s). 3DIC, page TS7.4.1-TS7.4.4. IEEE, (2015)New concept of TSV formation methodology using Directed Self-Assembly (DSA)., , , , , , , and . 3DIC, page 1-4. IEEE, (2016)Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration., , , , and . 3DIC, page 1-4. IEEE, (2019)Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration., , , , , , , , and . Micromachines, 7 (10): 184 (2016)Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology., , , , , and . 3DIC, page 1-4. IEEE, (2016)