( en | de | ru )

 

Disambiguation of "Peng, Xiaochen"

Author of the publication

copydeleteadd this publication to your clipboard
Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator.

, , , , , and . ISCAS, page 1-4. IEEE, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Xiaochen Hu

Xiaochen Lian

Xiao-Wei Peng

Changgeng Peng

Martin Peng

 

Other publications of authors with the same name

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online Learning., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (12): 3067-3080 (2018)Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic Devices., , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 37:1-37:19 (2022)XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption., , , , and . ICCAD, page 77:1-77:6. IEEE, (2020)Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning Accelerator.. Georgia Institute of Technology, Atlanta, GA, USA, (2022)base-search.net (ftgeorgiatech:oai:smartech.gatech.edu:1853/66465).Compute-in-Memory: From Device Innovation to 3D System Integration., , , , , , , and . ESSDERC, page 21-28. IEEE, (2021)Cryogenic Performance for Compute-in-Memory Based Deep Neural Network Accelerator., , , , , and . ISCAS, page 1-4. IEEE, (2021)Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging Memories., , , , and . DATE, page 1025-1030. IEEE, (2020)XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networks., , , , , and . DATE, page 1423-1428. IEEE, (2018)Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis., , , , , , , and . DAC, page 140. ACM, (2019)Parallelizing SRAM arrays with customized bit-cell for binary neural networks., , , , , , , , and . DAC, page 21:1-21:6. ACM, (2018)