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Disambiguation of "Pullela, Satyamurthy"

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Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.

, , and . DAC, page 165-170. ACM Press, (1993)

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Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization., , and . DAC, page 165-170. ACM Press, (1993)Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (2): 210-215 (1997)Clock Distribution Methodology for PowerPCTM Microprocessors., , and . VLSI Signal Processing, 16 (2-3): 181-189 (1997)Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor., , , , and . ICCD, page 143-148. IEEE Computer Society, (1997)RC interconnect synthesis-a moment fitting approach., , , and . ICCAD, page 418-425. IEEE Computer Society / ACM, (1994)Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization., , and . DAC, page 690-695. ACM Press, (1995)Library-less synthesis for static CMOS combinational logic circuits., , , , , , , and . ICCAD, page 658-662. IEEE Computer Society / ACM, (1997)Post-processing of clock trees via wiresizing and buffering for robust design., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (6): 691-701 (1996)Modeling the "Effective capacitance" for the RC interconnect of CMOS gates., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (12): 1526-1535 (1994)CMOS Combinational Circuit Sizing by Stage-wise Tapering., , , and . DATE, page 985-986. IEEE Computer Society, (1998)