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Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (10): 1637-1643 (2005)Delay analysis of CMOS gates using modified logical effort model., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (6): 937-947 (2005)Efficient Scheme for Implementing Large Size Signed Multipliers Using Multigranular Embedded DSP Blocks in FPGAs., , и . Int. J. Reconfigurable Comput., (2009)Efficient Realization of BCD Multipliers Using FPGAs., , , и . Int. J. Reconfigurable Comput., (2017)Efficient FPGA implementation of complex multipliers using the logarithmic number system., , и . ISCAS, стр. 3154-3157. IEEE, (2008)Energy delay analysis of partial product reduction methods for parallel multiplier implementation., , и . ISLPED, стр. 201-204. IEEE, (1996)Behavioural synthesis of low power floating point CORDIC processors., и . ICECS, стр. 506-509. IEEE, (2000)Low power floating point MAFs-a comparative study., , , и . ISSPA, стр. 284-287. IEEE, (2001)Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity., и . ISCAS (5), стр. 361-364. IEEE, (2002)Optimised realisations of large integer multipliers and squarers using embedded blocks., , , и . IET Comput. Digit. Tech., 1 (1): 9-16 (2007)