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Disambiguation of "Asada, Kunihiro"

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Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operation.

, , and . COOL Chips, page 1-3. IEEE Computer Society, (2012)

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Kunihiro Jojima

 

Other publications of authors with the same name

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator., , , and . CICC, page 1-4. IEEE, (2013)A Pulse Width controlled PLL and its automated design flow., , , and . ICECS, page 5-8. IEEE, (2013)On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure., , , , , and . ESSCIRC, page 183-186. IEEE, (2011)High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design., , , , , and . ASP-DAC, page 255-260. IEEE, (2013)Extension of power supply impedance emulation method on ATE for multiple power domain., , , , , , and . ETS, page 1-2. IEEE, (2017)Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology., , , , and . ICECS, page 220-223. IEEE, (2011)Timing-Aware Cell Layout De-Compaction for Yield Optimization by Critical Area Minimization., , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (6): 716-720 (2007)A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18-µm CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (1): 11-19 (2019)On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems., , , , and . IEICE Trans. Electron., 96-C (4): 560-567 (2013)Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter., and . IEICE Trans. Electron., 95-C (2): 297-302 (2012)