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STT-Based Non-Volatile Logic-in-Memory Framework., , and . Field-Coupled Nanocomputing, volume 8280 of Lecture Notes in Computer Science, Springer, (2014)Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies., , and . IEEE Trans. Very Large Scale Integr. Syst., 19 (4): 647-658 (2011)Design tool and methodologies for interconnect reliability analysis in integrated circuits.. Massachusetts Institute of Technology, Cambridge, MA, USA, (2004)ndltd.org (oai:dspace.mit.edu:1721.1/26722).Circuit Level Reliability Analysis of Cu Interconnects., , , and . ISQED, page 238-243. IEEE Computer Society, (2004)Ultra-Low Power Hybrid CMOS-Magnetic Logic Architecture., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (9): 2008-2016 (2012)Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints., , , and . IET Comput. Digit. Tech., 5 (3): 169-178 (2011)Adiabatic/MTJ-Based Physically Unclonable Function for Consumer Electronics Security., , and . IEEE Trans. Consumer Electron., 69 (1): 1-8 (February 2023)Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs., , and . ISQED, page 751-756. IEEE, (2011)Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput., , , , , , , , , and 15 other author(s). IMW, page 1-4. IEEE, (2022)Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs., , and . 3DIC, page 1-7. IEEE, (2009)