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Disambiguation of "Kundu, Sandip"

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An Architecture to Enable Life Cycle Testing in CMPs.

, , and . DFT, page 341-348. IEEE Computer Society, (2011)

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Sandip Agarwala

Arijit Kundu

Sandip Murarka

Sandip Roy

Sudip Kundu

 

Other publications of authors with the same name

Symbolic implication in test generation., , , and . EURO-DAC, page 492-496. EEE Computer Society, (1991)A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays., , and . IEEE Trans. Computers, 61 (7): 986-998 (2012)Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems., , and . IEEE Trans. Computers, 65 (3): 677-678 (2016)Preventing integrated circuit piracy via custom encoding of hardware instruction set., , and . ISQED, page 234-241. IEEE, (2016)Test Challenges in Nanometer Technologies., , , and . J. Electron. Test., 17 (3-4): 209-218 (2001)Pitfalls of hierarchical fault simulation.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 312-314 (2004)A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits., , and . ACM Great Lakes Symposium on VLSI, page 529-534. ACM, (2009)Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs., , , and . AsianHOST, page 25-30. IEEE, (2018)Abstraction-Guided Simulation Using Markov Analysis for Functional Verification., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (2): 285-297 (2016)A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering of Program Phases to Produce Temperature Extremes in a Chip., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (12): 1867-1880 (2012)