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Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment., , and . NATW, page 1-4. IEEE, (2017)On linewidth-based yield analysis for nanometer lithography., and . DATE, page 381-386. IEEE, (2009)A study on placement of post silicon clock tuning buffers for mitigating impact of process variation., and . DATE, page 292-295. IEEE, (2009)On Enhancing Reliability of Weak PUFs via Intelligent Post-Silicon Accelerated Aging., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (3): 960-969 (2018)A Pattern Generation Technique for Maximizing Switching Supply Currents Considering Gate Delays., , and . IEEE Trans. Computers, 61 (7): 986-998 (2012)Symbolic implication in test generation., , , and . EURO-DAC, page 492-496. EEE Computer Society, (1991)Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems., , and . IEEE Trans. Computers, 65 (3): 677-678 (2016)Preventing integrated circuit piracy via custom encoding of hardware instruction set., , and . ISQED, page 234-241. IEEE, (2016)Critical area driven dummy fill insertion to improve manufacturing yield., and . ISQED, page 334-341. IEEE, (2012)Test Challenges in Nanometer Technologies., , , and . J. Electron. Test., 17 (3-4): 209-218 (2001)