Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA., , , , , , and . FPT, page 370-373. IEEE, (2014)Modular arithmetic decision procedure with auto-correction mechanism., and . HLDVT, page 138-145. IEEE Computer Society, (2009)A formal approach to debug polynomial datapath designs.. ASP-DAC, page 683-688. IEEE, (2012)Data-path aware high-level ECO synthesis., , and . Integr., (2019)A Formal Approach for Debugging Arithmetic Circuits., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 742-754 (2009)Aggressive overclocking support using a novel timing error recovery technique on FPGAs (abstract only)., , and . FPGA, page 288. ACM, (2010)High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization., , and . ICRC, page 1-10. IEEE, (2018)Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions., and . ATVA, volume 4762 of Lecture Notes in Computer Science, page 129-144. Springer, (2007)Low power scheduling in high-level synthesis using dual-Vth library., , and . ISQED, page 507-511. IEEE, (2015)Binary Taylor diagrams: an efficient implementation of Taylor expansion diagrams., , , , , , and . ISCAS (1), page 424-427. IEEE, (2005)