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Disambiguation of "Okumura, Shunsuke"

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A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells.

, , , and . ASP-DAC, page 79-80. IEEE, (2013)

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Shunsuke Saito

 

Other publications of authors with the same name

0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM., , , and . ISLPED, page 219-224. ACM, (2010)Bit error rate estimation in SRAM considering temperature fluctuation., , , , , , , and . ISQED, page 516-519. IEEE, (2012)Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units., , , , , , , and . DSN Workshops, page 91-96. IEEE Computer Society, (2011)A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction., , , , , , and . ISQED, page 489-492. IEEE, (2012)Quality of a Bit (QoB): A New Concept in Dependable SRAM., , , , , , and . ISQED, page 98-102. IEEE Computer Society, (2008)7T SRAM enabling low-energy simultaneous block copy., , , , , and . CICC, page 1-4. IEEE, (2010)Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential., , , , , , and . Inf. Media Technol., 6 (2): 296-306 (2011)A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing., , , , , , , and . IEICE Trans. Electron., 91-C (4): 543-552 (2008)7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory., , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 94-A (12): 2693-2700 (2011)A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique., , , , , , and . ASP-DAC, page 77-78. IEEE, (2013)