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22.5 A 4×20Gb/s WDM ring-based hybrid CMOS silicon photonics transceiver., , , , , , , , , and 6 other author(s). ISSCC, page 1-3. IEEE, (2015)Impact of interface state trap density on the performance characteristics of different III-V MOSFET architectures., , , , , , , , and . Microelectron. Reliab., 50 (3): 360-364 (2010)Lateral NWFET optimization for beyond 7nm nodes., , , , , , , , , and 3 other author(s). ICICDT, page 1-4. IEEE, (2015)An analytical compact model for estimation of stress in multiple Through-Silicon Via configurations., , , , , , , , , and . DATE, page 505-506. IEEE, (2011)3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV)., , , , , , , , , and 3 other author(s). 3DIC, page 1-5. IEEE, (2009)Mechanism of O2-anneal induced Vfb shifts of Ru gated stacks., , , , , , , , , and 5 other author(s). Microelectron. Reliab., 47 (4-5): 518-520 (2007)Measurement and Analysis of Parasitic Capacitance in FinFETs with High-k Dielectrics and Metal-Gate Stack., , , , and . VLSI Design, page 253-258. IEEE Computer Society, (2009)The relationship between border traps characterized by AC admittance and BTI in III-V MOS devices., , , , , , , , , and 2 other author(s). IRPS, page 5. IEEE, (2015)Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter., , , , , , , , , and 1 other author(s). OFC/NFOEC, page 1-3. IEEE, (2013)Scaling considerations of the constitutive equations in a 2-D finite element heterojunction simulator PRISM., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (11): 1786-1797 (1993)