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Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

A. Phommahaxay, A. Jourdain, G. Verbinnen, T. Woitke, P. Bisson, M. Gabriel, W. Spiess, A. Guerrero, J. McCutcheon, R. Puligadda, P. Bex, A. den Eede, B. Swinnen, G. Beyer, A. Miller, and E. Beyne. 3DIC, page 1-4. IEEE, (2011)

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Alain Schifferli

Alain Durocher

Alain Lory

Alain Schlichting

Alain Villard

Other publications of authors with the same name

Protective Layer for Collective Die to Wafer Hybrid Bonding.F. Inoue, J. Bertheau, S. Suhard, A. Phommahaxay, T. Ohashi, T. Kinoshita, Y. Kinoshita, and E. Beyne. 3DIC, page 1-4. IEEE, (2019)300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications.A. Jourdain, T. Buisson, A. Phommahaxay, M. Privett, D. Wallace, S. Sood, P. Bisson, E. Beyne, Y. Travaly, and B. Swinnen. 3DIC, page 1-4. IEEE, (2010)In-line metrology and inspection for process control during 3D stacking of IC's.S. Halder, I. Wolf, A. Phommahaxay, A. Miller, M. Maenhoudt, G. Beyer, B. Swinnen, and E. Beyne. 3DIC, page 1-4. IEEE, (2011)Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.A. Phommahaxay, A. Jourdain, G. Verbinnen, T. Woitke, P. Bisson, M. Gabriel, W. Spiess, A. Guerrero, J. McCutcheon, R. Puligadda and 6 other author(s). 3DIC, page 1-4. IEEE, (2011)Design issues and considerations for low-cost 3D TSV IC technology.G. der Plas, P. Limaye, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis and 24 other author(s). ISSCC, page 148-149. IEEE, (2010)Process Complexity and Cost Considerations of Multi-Layer Die Stacks.D. Velenis, J. Vos, S. Kim, J. Derakhshandeh, P. Bex, G. Capuz, S. Suhard, K. Rebibis, S. Huylenbroeck, E. Marinissen and 5 other author(s). 3DIC, page 1-6. IEEE, (2019)Importance of alignment control during permanent bonding and its impact on via-last alignment for high density 3D interconnects.J. Vos, L. Peng, A. Phommahaxay, J. Ongeval, A. Miller, E. Beyne, F. Kurz, T. Wagenleiter, M. Wimplinger, and T. Uhrmann. 3DIC, page 1-5. IEEE, (2016)

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Disambiguation of "Phommahaxay, Alain"

Please choose a person to relate this publication to

Alain Schifferli

Alain Durocher

Alain Lory

Alain Schlichting

Alain Villard

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Phommahaxay, Alain"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultrathin wafer handling in 3D Stacked IC manufacturing combining a novel ZoneBOND™ temporary bonding process with room temperature peel debonding.

Please choose a person to relate this publication to

Alain Schifferli

Alain Durocher

Alain Lory

Alain Schlichting

Alain Villard

Other publications of authors with the same name

Disambiguation