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Disambiguation of "Toyoshima, Hideo"

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FeRAM device and circuit technologies fully compatible with advanced CMOS.

, , , , , , , , , , , and . CICC, page 171-178. IEEE, (2001)

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Hideo Baba

Hideo Ohashi

Hideo Andreas Baba

Hideo Ikezawa-Hanada

 

Other publications of authors with the same name

FeRAM device and circuit technologies fully compatible with advanced CMOS., , , , , , , , , and 2 other author(s). CICC, page 171-178. IEEE, (2001)NV-SRAM: a nonvolatile SRAM with backup ferroelectric capacitors., , , , , , , , , and . IEEE J. Solid State Circuits, 36 (3): 522-527 (2001)A 500-MHz 4-Mb CMOS pipeline-burst cache SRAM with point-to-point noise reduction coding I/O., , , , , , , , , and . IEEE J. Solid State Circuits, 32 (11): 1758-1765 (1997)A 128-kb FeRAM macro for contact/contactless smart-card microcontrollers., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 37 (8): 1073-1079 (2002)An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors., , , , , , , , , and . CICC, page 65-68. IEEE, (2000)A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cell with PMOS access transistors., , , , , , , , , and . IEEE J. Solid State Circuits, 30 (11): 1196-1202 (November 1995)A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM., , , , , , , , and . IEEE J. Solid State Circuits, 31 (11): 1610-1617 (1996)A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (11): 1631-1640 (2000)An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , and 2 other author(s). CICC, page 283-286. IEEE, (2000)