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The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , и . IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)

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Carl W David

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Другие публикации лиц с тем же именем

A low-jitter PLL clock generator for microprocessors with lock range of 340-612 MHz.. IEEE J. Solid State Circuits, 34 (4): 513-519 (1999)On-chip circuit for measuring multi-GHz clock signal waveforms., , , , , и . VTS, стр. 1-4. IEEE Computer Society, (2013)True hardware random number generation implemented in the 32-nm SOI POWER7+ processor., , , , , , , и . IBM J. Res. Dev., (2013)IBM Enterprise Systems multimode fiber optic technology., , , , , , , , , и . IBM J. Res. Dev., 36 (4): 553-576 (1992)A clock distribution network for microprocessors., , , , , , , , , и 6 other автор(ы). IEEE J. Solid State Circuits, 36 (5): 792-799 (2001)The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking., , , , , , , , , и 20 other автор(ы). IEEE J. Solid State Circuits, 50 (1): 10-23 (2015)A Circuit for Reducing Large Transient Current Effects on Processor Power Grids., , , , , и . ISSCC, стр. 2238-2245. IEEE, (2006)