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Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.

, , , , , и . J. Electron. Test., 29 (3): 401-413 (2013)

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Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Rajesh Chitta

Rajesh Saiju

Rajesh Narasimha

Rajesh Kolli

 

Другие публикации лиц с тем же именем

Test Roles in Diagnosis and Silicon Debug., , , , , , и . ATS, стр. 367. IEEE, (2007)A low-cost concurrent error detection technique for processor control logic., , , , и . DATE, стр. 897-902. ACM, (2008)Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 238-246 (2017)Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder., , , , , и . J. Electron. Test., 29 (3): 401-413 (2013)Session Abstract., и . VTS, стр. 422-423. IEEE Computer Society, (2006)Path coverage based functional test generation for processor marginality validation., , , и . ITC, стр. 544-552. IEEE Computer Society, (2010)Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic., , , , и . ETS, стр. 171-176. IEEE Computer Society, (2008)Testing in the year 2020., , и . DATE, стр. 960-965. EDA Consortium, San Jose, CA, USA, (2007)Test Challenges in Nanometer Technologies., , , и . J. Electron. Test., 17 (3-4): 209-218 (2001)An automatic test pattern generation program for large ASICs., , и . ICCD, стр. 244-248. IEEE, (1989)