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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.

R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, K. Xu, V. Georgiev, K. Ni, P. Debacker, A. Asenov, and A. Todri-Sanial. IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 432-439 (2022)

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Johann Christoph Petersenn

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Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.N. Laubeuf, J. Doevenspeck, I. Papistas, M. Caselli, S. Cosemans, P. Vrancx, D. Bhattacharjee, A. Mallik, P. Debacker, D. Verkest and 2 other author(s). ACM Trans. Design Autom. Electr. Syst., 27 (5): 46:1-46:21 (2022)Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes.P. Debacker, K. Han, A. Kahng, H. Lee, P. Raghavan, and L. Wang. DAC, page 51:1-51:6. ACM, (2017)Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.R. Chen, L. Chen, J. Liang, Y. Cheng, S. Elloumi, J. Lee, K. Xu, V. Georgiev, K. Ni, P. Debacker and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 432-439 (2022)How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node?B. Ku, P. Debacker, D. Milojevic, P. Raghavan, and S. Lim. ICCAD, page 87. ACM, (2016)A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.T. Evenblij, C. Tenllado, M. Perumkunnil, F. Catthoor, S. Sakhare, P. Debacker, G. Kar, A. Furnémont, N. Bueno, and J. Pérez. ICCD, page 255-263. IEEE, (2019)Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation.M. Caselli, D. Bhattacharjee, A. Mallik, P. Debacker, and D. Verkest. ISCAS, page 1823-1827. IEEE, (2022)Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator.S. Majumdar, S. Cosemans, A. Mallik, P. Debacker, F. Catthoor, and J. Houdt. ISCAS, page 1-5. IEEE, (2023)Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route.G. Sisto, P. Debacker, R. Chen, G. der Plas, R. Chou, E. Beyne, and D. Milojevic. 3DIC, page 1-4. IEEE, (2019)Power Estimation at Different Abstraction Levels for Wireless Baseband Processors.M. Palkovic, P. Debacker, P. Avasare, S. Dupont, and T. Aa. J. Low Power Electron., 8 (5): 726-738 (2012)AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.S. Yang, D. Bhattacharjee, V. Kumar, S. Chatterjee, S. De, P. Debacker, D. Verkest, A. Mallik, and F. Catthoor. IEEE J. Emerg. Sel. Topics Circuits Syst., 12 (2): 508-521 (2022)

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Disambiguation of "Debacker, Peter"

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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.

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Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Johann Christoph Petersenn

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BibSonomy

Disambiguation of "Debacker, Peter"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.

Please choose a person to relate this publication to

Tanja Elisabeth Peters

Andre Peters

Jillian Petersen

Robert Martin Peterreins

Johann Christoph Petersenn

Other publications of authors with the same name

Disambiguation

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Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization.