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Disambiguation of "Yotsuyanagi, Hiroyuki"

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On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.

, , , , and . DELTA, page 269-274. IEEE Computer Society, (2004)

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Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Okamuro

Hiroyuki Takada

Hiroyuki Isobe

 

Other publications of authors with the same name

Electric field for detecting open leads in CMOS logic circuits by supply current testing., , , and . ISCAS (3), page 2995-2998. IEEE, (2005)A supply current testable register string DAC of decoder type., , , and . ISCIT, page 58-63. IEEE, (2011)Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture., , and . 3DIC, page 1-6. IEEE, (2011)Sequential Redundancy Removal Using Test Generation and Multiple Unreachable States., , , and . Asian Test Symposium, page 23-. IEEE Computer Society, (2001)Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories., , , and . ATS, page 254-259. IEEE Computer Society, (2017)Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs., , , , and . ATS, page 242-247. IEEE Computer Society, (2017)Testability Analysis of IDDQ Testing with Large Threshold Value., , , and . DFT, page 367-375. IEEE Computer Society, (2000)Random Pattern Testability of the Open Defect Detection Method using Application of Time-variable Electric Field., , , , and . DELTA, page 387-391. IEEE Computer Society, (2002)Identification and Frequency Estimation of Feedback Bridging Faults Generating Logical Oscillation in CMOS Circuits., , and . IEICE Trans. Inf. Syst., 87-D (3): 571-579 (2004)On Detecting Delay Faults Using Time-to-Digital Converter Embedded in Boundary Scan., , , and . IEICE Trans. Inf. Syst., 96-D (9): 1986-1993 (2013)