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A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.

C. Jan, F. Al amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl, S. Shi, K. Komeyli, H. Kilambi, A. Kumar, K. Byon, C. Lee, J. Lee, T. Leo, P. Liu, N. Nidhi, R. Olac vaw, C. Petersburg, K. Phoa, C. Prasad, C. Quincy, R. Ramaswamy, T. Rana, L. Rockford, A. Subramaniam, C. Tsai, P. Vandervoorn, L. Yang, A. Zainuddin, and P. Bai. VLSIC, page 12-. IEEE, (2015)

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Olindo Chiaffarelli

Martina Chiari

Armando Aníbal Chiappe

Hsin-yi Chiang

Yi-Chang Chiang

Other publications of authors with the same name

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.H. Lakdawala, M. Schaecher, C. Fu, R. Limaye, J. Duster, Y. Tan, A. Balankutty, E. Alpman, C. Lee, K. Nguyen and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)Moore's law - predict the unpredictable.C. Jan. VLSI-DAT, page 1. IEEE, (2018)A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for low power, high performance and high density SoC products.C. Jan, F. Al amoody, H. Chang, T. Chang, Y. Chen, N. Dias, W. Hafez, D. Ingerly, M. Jang, E. Karl and 24 other author(s). VLSIC, page 12-. IEEE, (2015)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.H. Lakdawala, M. Schaecher, C. Fu, R. Limaye, J. Duster, Y. Tan, A. Balankutty, E. Alpman, C. Lee, S. Suzuki and 13 other author(s). ISSCC, page 62-64. IEEE, (2012)A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.Y. Wang, H. Ahn, U. Bhattacharya, T. Coan, F. Hamzaoglu, W. Hafez, C. Jan, P. Kolar, S. Kulkarni, J. Lin and 6 other author(s). ISSCC, page 324-606. IEEE, (2007)A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.Y. Wang, H. Ahn, U. Bhattacharya, Z. Chen, T. Coan, F. Hamzaoglu, W. Hafez, C. Jan, P. Kolar, S. Kulkarni and 7 other author(s). IEEE J. Solid State Circuits, 43 (1): 172-179 (2008)

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Disambiguation of "Jan, Chia-Hong"