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Block-Wise Dynamic-Precision Neural Network Training Acceleration via Online Quantization Sensitivity Analytics.

, , , , , and . CoRR, (2022)

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STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 55 (2): 465-477 (2020)GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing., , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 640-653 (2019)Performance-centric register file design for GPUs using racetrack memory., , , , , , , and . ASP-DAC, page 25-30. IEEE, (2016)Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture., , , , , , and . DAC, page 80:1-80:6. ACM, (2017)Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor., , , , , and . DAC, page 184:1-184:6. ACM, (2015)Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration., , , , , , and . DAC, page 126:1-126:6. ACM, (2015)A Ferroelectric Nonvolatile Processor with 46 $$ s System-Level Wake-up Time and 14 $$ s Sleep Time for Energy Harvesting Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (3): 596-607 (2017)Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks., , , and . IEICE Trans. Commun., 93-B (9): 2299-2308 (2010)Register allocation for hybrid register architecture in nonvolatile processors., , , , , and . ISCAS, page 1050-1053. IEEE, (2014)An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)