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2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters., , , , , , , , , and 18 other author(s). ISSCC, page 46-48. IEEE, (2020)Thermo-mechanical study of a 2.5D passive silicon interposer technology: Experimental, numerical and In-Situ stress sensors developments., , , , , , , , , and 1 other author(s). 3DIC, page 1-7. IEEE, (2013)Heat spreading packaging solutions for hybrid bonded 3D-ICs., , , , , , , , , and 2 other author(s). 3DIC, page 1-6. IEEE, (2016)Using TSVs for thermal mitigation in 3D circuits: Wish and truth., , , , , , , , , and 1 other author(s). 3DIC, page 1-8. IEEE, (2014)3D integration demonstration of a wireless product with design partitioning., , , , , , , , , and 17 other author(s). 3DIC, page 1-5. IEEE, (2011)Recent progress in Silicon Photonics R&D and manufacturing on 300mm wafer platform., , , , , , , , , and 18 other author(s). OFC, page 1-3. IEEE, (2015)Influence of 3D integration on 2D interconnections and 2D self inductors HF properties., , , , , , and . 3DIC, page 1-6. IEEE, (2009)Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits., , , , , , , , , and 3 other author(s). 3DIC, page 1-7. IEEE, (2009)Device and electromagnetic co-simulation of TSV: Substrate noise study and compact modeling of a TSV in a matrix., , , and . ISQED, page 404-411. IEEE, (2012)Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability., , , , , , , , , and 7 other author(s). IRPS, page 4. IEEE, (2018)