( en | de | ru )

 

Disambiguation of "Borkar, Nitin"

Author of the publication

copydeleteadd this publication to your clipboard
Resiliency for many-core system on a chip.

, , , , , , and . ASP-DAC, page 388-389. IEEE, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Milind Borkar

Sirin Nitinawarat

Nitin Nangare

Nitin Suresh

Sachin Borkar

 

Other publications of authors with the same name

An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS., , , , , , , , , and 4 other author(s). ISSCC, page 98-589. IEEE, (2007)A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS., , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 757-766 (2011)System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3468-3476 (2016)Design Challenges in Sub-100nm High Performance Microprocessors., , , and . VLSI Design, page 15-17. IEEE Computer Society, (2004)Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 46 (1): 184-193 (2011)A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS., , , , , , , , , and 3 other author(s). ISSCC, page 2572-2581. IEEE, (2006)A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm., , , , , , and . VLSI Design, page 252-257. IEEE Computer Society, (2010)Process, Temperature, and Supply-Noise Tolerant 45nm Dense Cache Arrays With Diffusion-Notch-Free (DNF) 6T SRAM Cells and Dynamic Multi-Vcc Circuits., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 44 (4): 1199-1208 (2009)A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization., , , and . IEEE J. Solid State Circuits, 41 (10): 2314-2323 (2006)An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 43 (1): 29-41 (2008)