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A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems., , , , и . PIMRC, стр. 531-535. IEEE, (2004)Power analysis and estimation tool integrated with XPOWER., , , и . FPGA, стр. 259. ACM, (2004)Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain., , и . Int. J. Reconfigurable Comput., (2014)50 Years of CORDIC: Algorithms, Architectures, and Applications., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1893-1907 (2009)FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices., , , , , и . IEEE Trans. Educ., 50 (3): 229-235 (2007)Low-complexity low-density parity check decoding algorithm for high-speed very large scale integration implementation., , , и . IET Commun., 6 (16): 2575-2581 (2012)Efficient FPGA-implementation of two's complement digit-serial/parallel multipliers., и . IEEE Trans. Circuits Syst. II Express Briefs, 50 (6): 317-322 (2003)A 630 Mbps non-binary LDPC decoder for FPGA., , , , и . ISCAS, стр. 1989-1992. IEEE, (2015)Design of high performance timing recovery loops for communication applications., , , и . SiPS, стр. 1-4. IEEE, (2006)Low latency T-EMS decoder for non-binary LDPC codes., , , , , и . ACSSC, стр. 831-835. IEEE, (2013)