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Disambiguation of "Horiguchi, Naoto"

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Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending.

, , , , , , , and . IRPS, page 1-5. IEEE, (2019)

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Naoto Kamano

Naoto Matsumura

Tomonaga Horiguchi

 

Other publications of authors with the same name

Off-state stress degradation mechanism on advanced p-MOSFETs., , , , , , , , and . ICICDT, page 1-4. IEEE, (2015)Assessment of SiGe quantum well transistors for DRAM peripheral applications., , , , , , , , , and 1 other author(s). ICICDT, page 1-4. IEEE, (2015)Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors., , , , , , , , , and 8 other author(s). ESSDERC, page 190-193. IEEE, (2013)Origins and implications of increased channel hot carrier variability in nFinFETs., , , , , , , , , and 11 other author(s). IRPS, page 3. IEEE, (2015)Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation., , , , , , , , and . IRPS, page 1-6. IEEE, (2020)Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors., , , , , , , and . ASICON, page 1-4. IEEE, (2019)Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails., , , , , , , , , and 34 other author(s). VLSI Technology and Circuits, page 284-285. IEEE, (2022)Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO., , , , , , , , , and 3 other author(s). VLSI Technology and Circuits, page 431-432. IEEE, (2022)Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps., , , , , , , , and . IRPS, page 1-6. IEEE, (2021)PPAC scaling enablement for 5nm mobile SoC technology., , , , , , , , , and 7 other author(s). ESSDERC, page 240-243. IEEE, (2017)