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Disambiguation of "Wong, S. Simon"

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A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications.

, , , , , and . ISSCC, page 564-622. IEEE, (2007)

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Simon S Lee

Walter Wong

Limsoon Wong

Hoi-Ming Wong

Yasert Wongthonglua

 

Other publications of authors with the same name

Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory., , , , and . ISSCC, page 406-408. IEEE, (2012)Analysis and Design of a Passive Switched-Capacitor Matrix Multiplier for Approximate Computing., and . CoRR, (2016)24.2 A 2.5GHz 7.7TOPS/W switched-capacitor matrix multiplier with co-designed local memory in 40nm., and . ISSCC, page 418-419. IEEE, (2016)Impact of III-V and Ge Devices on Circuit Performance., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (7): 1189-1200 (2013)Exploiting CMOS reverse interconnect scaling in multigigahertz amplifier and oscillator design., , , , , and . IEEE J. Solid State Circuits, 36 (10): 1480-1488 (2001)Deep COVID DeteCT: an international experience on COVID-19 lung detection and prognosis using chest CT., , , , , , , , , and 19 other author(s). npj Digit. Medicine, (2021)Design Strategy of On-Chip Inductors for Highly Integrated RF Systems., and . DAC, page 982-987. ACM Press, (1999)Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array., , , and . JETC, 9 (1): 9:1-9:14 (2013)Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (9): 907-911 (2008)Optimization of Driver Preemphasis for On-Chip Interconnects., and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 2033-2041 (2009)