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A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.

J. Carballido, J. Hermosillo, A. Veloz-Guerrero, D. Arditti, A. Rio, E. Sandoval, M. Guzman-Renteria, H. Lakdawala, and M. Verhelst. IEEE J. Solid State Circuits, 48 (7): 1669-1679 (2013)

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Zahra Lakdawala

Hasnain Raza

Chang-Hasnain

Hasnain Ghazi

Syed Nazrul Hasnain

Other publications of authors with the same name

A 5 GHz class-AB power amplifier in 90 nm CMOS with digitally-assisted AM-PM correction.Y. Palaskas, S. Taylor, S. Pellerano, I. Rippke, R. Bishop, A. Ravi, H. Lakdawala, and K. Soumyanath. CICC, page 813-816. IEEE, (2005)A 0.5 mm2 integrated capacitive vibration sensor with sub-10 zF/rt-Hz noise floor.S. Iyer, H. Lakdawala, R. Sinha, E. Zacherl, R. Unetich, D. Gaugel, D. Guillou, and L. Carley. CICC, page 93-96. IEEE, (2005)32nm x86 OS-compliant PC on-chip with dual-core Atom® processor and RF WiFi transceiver.H. Lakdawala, M. Schaecher, C. Fu, R. Limaye, J. Duster, Y. Tan, A. Balankutty, E. Alpman, C. Lee, S. Suzuki and 13 other author(s). ISSCC, page 62-64. IEEE, (2012)A flip-chip-packaged 1.8V 28dBm class-AB power amplifier with shielded concentric transformers in 32nm SoC CMOS.Y. Tan, H. Xu, M. El-Tanani, S. Taylor, and H. Lakdawala. ISSCC, page 426-428. IEEE, (2011)A 2.4GHz WLAN transceiver with fully-integrated highly-linear 1.8V 28.4dBm PA, 34dBm T/R switch, 240MS/s DAC, 320MS/s ADC, and DPLL in 32nm SoC CMOS.Y. Tan, J. Duster, C. Fu, E. Alpman, A. Balankutty, C. Lee, A. Ravi, S. Pellerano, K. Chandrashekar, H. Kim and 5 other author(s). VLSIC, page 76-77. IEEE, (2012)A Class-E PA With Pulse-Width and Pulse-Position Modulation in 65 nm CMOS.J. Walling, H. Lakdawala, Y. Palaskas, A. Ravi, O. Degani, K. Soumyanath, and D. Allstot. IEEE J. Solid State Circuits, 44 (6): 1668-1678 (2009)A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.J. Carballido, J. Hermosillo, A. Veloz-Guerrero, D. Arditti, A. Rio, E. Sandoval, M. Guzman-Renteria, H. Lakdawala, and M. Verhelst. IEEE J. Solid State Circuits, 48 (7): 1669-1679 (2013)A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver.H. Lakdawala, M. Schaecher, C. Fu, R. Limaye, J. Duster, Y. Tan, A. Balankutty, E. Alpman, C. Lee, K. Nguyen and 16 other author(s). IEEE J. Solid State Circuits, 48 (1): 91-103 (2013)An in-situ temperature-sensing interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-temperature compensation of crystal oscillators.Z. Wang, R. Lin, E. Gordon, H. Lakdawala, L. Carley, and J. Jensen. ISSCC, page 316-317. IEEE, (2010)A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS.T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and U. Moon. CICC, page 1-4. IEEE, (2009)

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Disambiguation of "Lakdawala, Hasnain"

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A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.

Please choose a person to relate this publication to

Zahra Lakdawala

Hasnain Raza

Chang-Hasnain

Hasnain Ghazi

Syed Nazrul Hasnain

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lakdawala, Hasnain"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.

Please choose a person to relate this publication to

Zahra Lakdawala

Hasnain Raza

Chang-Hasnain

Hasnain Ghazi

Syed Nazrul Hasnain

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

A Programmable Calibration/BIST Engine for RF and Analog Blocks in SoCs Integrated in a 32 nm CMOS WiFi Transceiver.