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A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator., , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (7): 2094-2106 (2022)A New Cellular-Based Redundant TSV Structure for Clustered Faults., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 27 (2): 458-467 (2019)Frequency Attention Network: Blind Noise Removal for Real Images., , , , , и . ACCV (2), том 12623 из Lecture Notes in Computer Science, стр. 168-184. Springer, (2020)MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5., , , , , , и . ASICON, стр. 1-4. IEEE, (2023)Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture., , , , , , и . DATE, стр. 1394-1399. IEEE, (2021)Boosting ReRAM-based DNN by Row Activation Oversubscription., , , , и . ASP-DAC, стр. 604-609. IEEE, (2022)RTMDet-R2: An Improved Real-Time Rotated Object Detector., , , , , , и . PRCV (12), том 14436 из Lecture Notes in Computer Science, стр. 352-364. Springer, (2023)Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm., , , и . IPDPS Workshops, стр. 425-430. IEEE Computer Society, (2012)A novel low power 64-kb SRAM using bit-lines charge-recycling and non-uniform cell scheme., , , , и . ICECS, стр. 528-531. IEEE, (2011)Deploying and Optimizing Convolutional Neural Networks on Heterogeneous Architecture., , , , , , и . ASICON, стр. 1-4. IEEE, (2019)