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Disambiguation of "Ito, Shinya"

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Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs.

, , , , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 806-814 (2011)

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Shinya Sato

Shinya Minegishi

Nobutaka Ito

Takao Ito

Akio Ito

 

Other publications of authors with the same name

A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications., , , , , , , , , and 7 other author(s). ISSCC, page 212-597. IEEE, (2007)A method of digital watermarking by using the frequency masking effect., and . Syst. Comput. Jpn., 37 (11): 79-87 (2006)An ultra-high-density high-speed loadless four-transistor SRAM macro with a dual-layered twisted bit-line and a triple-well shield., , , , , , , , , and 2 other author(s). CICC, page 283-286. IEEE, (2000)Consumed-energy-type-aware routing for wireless sensor networks., and . WTS, page 1-6. IEEE, (2007)Exponentially Aggressive Preservation of Nearly Depleted Nodes for Wireless Sensor Networks., and . ITNG, page 880-882. IEEE Computer Society, (2007)Effect of mechanical stress induced by etch-stop nitride: impact on deep-submicron transistor performance., , , , , , , , and . Microelectron. Reliab., 42 (2): 201-209 (2002)The Microarchitecture of the CUE-v2 Processor: Enabling the Simultaneous Processing of Dataflow and Control-Flow Threads., , , and . PDPTA, page 525-531. CSREA Press, (2004)An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 36 (3): 510-515 (2001)Nonlinear visuoauditory integration in the mouse superior colliculus., , , and . PLoS Comput. Biol., (2021)A Self-evolutionary Emulation Scheme for A Networking Oriented Data-driven Processor Architecture: CUE., , and . PDPTA, page 1082-1088. CSREA Press, (2002)