( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Active and nonlinear wave propagation devices in ultrafast electronics and optoelectronics.

, , , , , , , , , , и . Proc. IEEE, 82 (7): 1037-1059 (1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Subhamoy Bhattacharya

Chhaya Bhattacharya

Nupur Bhattacharya

Indrajit Bhattacharya

Asitesh Bhattacharya

 

Другие публикации лиц с тем же именем

A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS Technology With Capacitive Charge-Sharing Write Assist Circuitry., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 51 (1): 222-229 (2016)Contention free delayed keeper for high density large signal sensing memory compiler., , и . Integr., (2018)A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation., , , , , , , и . ISSCC, стр. 346-347. IEEE, (2010)A 153Mb-SRAM Design with Dynamic Stability Enhancement and Leakage Reduction in 45nm High-Κ Metal-Gate CMOS Technology., , , , , , , , , и . ISSCC, стр. 376-377. IEEE, (2008)A 0.9um2 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating., , , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)A 0.9-μm2 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming., , , , , и . IEEE J. Solid State Circuits, 52 (4): 933-939 (2017)A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management., , , , , , , , и . IEEE J. Solid State Circuits, 45 (1): 103-110 (2010)An 18-Mb, 12.3-GB/s CMOS pipeline-burst cache SRAM with 1.54 Gb/s/pin., , , , , , , , и . IEEE J. Solid State Circuits, 34 (11): 1564-1570 (1999)A 0.094um2 high density and aging resilient 8T SRAM with 14nm FinFET technology featuring 560mV VMIN with read and write assist., , , , , и . VLSIC, стр. 266-. IEEE, (2015)A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry., , , , , , , , , и 1 other автор(ы). IEEE J. Solid State Circuits, 48 (1): 150-158 (2013)