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Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model.

S. Ma, Y. Wang, X. Chen, T. Wu, X. Wang, H. Tang, Y. Yao, H. Yu, Y. Sheng, J. Ma, J. Ren, and W. Bao. IEEE Access, (2020)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Shunli Zheng

Yuzhao Ma

Characterization of higher order modes in optical fibersY. Ma. Uni Erlangen-Nürnberg, (2009)

Tsie Ma

Jingxiang Ma

Lan Ma

Other publications of authors with the same name

A wide-division-ratio 100MHz-to-5GHz multi-modulus divider chain for wide-band PLL.F. An, S. Ma, Q. Chen, G. Zhou, F. Ye, and J. Ren. ASICON, page 1-4. IEEE, (2015)A 7GHz-bandwidth 31.5 GHz FMCW-PLL with novel twin-VCOs structure in 65nm CMOS.S. Ma, J. Sheng, N. Li, and J. Ren. A-SSCC, page 321-324. IEEE, (2017)A 10-18 GHz GaN Power Amplifier Based on Asymmetric Magnetically Coupled Resonator.J. Zhang, L. Nie, S. Ma, and J. Ren. MWSCAS, page 802-805. IEEE, (2020)A 5-10-Gb/s 12.5-mW Source Synchronous I/O Interface With 3-D Flip Chip Package.S. Ma, H. Yu, Q. Gu, and J. Ren. IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (2): 555-568 (2019)An Efficient NIZK Scheme for Privacy-Preserving Transactions over Account-Model Blockchain.S. Ma, Y. Deng, D. He, J. Zhang, and X. Xie. IACR Cryptol. ePrint Arch., (2017)A 23- to 28-GHz 5-bit switch-type phase shifter with 1-bit calibration based on optimized ABCD matrix design methods for 5G MIMO system in 0.15-μm GaAs.Z. Zhang, L. Nie, J. Zhang, T. Wu, Y. Chen, J. Ren, and S. Ma. Int. J. Circuit Theory Appl., 50 (6): 1834-1854 (2022)A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC With Efficient Depth Engine for Realtime LiDAR Systems.M. Sun, Y. Cao, J. Qian, J. Li, S. Zhou, Z. Zhao, Y. Wu, T. Xia, Y. Qin, L. Qiu and 3 other author(s). IEEE Trans. Circuits Syst. II Express Briefs, 70 (5): 1704-1708 (May 2023)A 60-GHz CMOS Balanced Power Amplifier with Miniaturized Quadrature Hybrids Achieving 19.0-dBm Output Power and 24.4% Peak PAE.Z. Zhang, X. Wang, Y. Chen, J. Ren, and S. Ma. APCCAS, page 560-564. IEEE, (2022)A Multi-channel 12-bits 100MS/s SAR ADC in 65nm CMOS.Y. Wei, T. Wu, S. Ma, and J. Ren. ASICON, page 1-4. IEEE, (2023)A 30-GHz to 39-GHz mm-Wave low-power injection-locked frequency divider in 65nm CMOS.G. Zhou, S. Ma, F. An, N. Li, F. Ye, and J. Ren. ASICON, page 1-4. IEEE, (2015)

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Disambiguation of "Ma, Shunli"

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Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model.

Please choose a person to relate this publication to

Shunli Zheng

Yuzhao Ma

Tsie Ma

Jingxiang Ma

Lan Ma

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ma, Shunli"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model.

Please choose a person to relate this publication to

Shunli Zheng

Yuzhao Ma

Tsie Ma

Jingxiang Ma

Lan Ma

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Analog Integrated Circuits Based on Wafer-Level Two-Dimensional MoS2 Materials With Physical and SPICE Model.