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A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.

Z. Wang, J. Yue, C. He, Z. Dai, F. Xiang, Z. Cong, Y. He, X. Feng, and Y. Liu. ISCAS, page 1-5. IEEE, (2023)

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Liu Liu

Dongmei Liu

Yinghao Liu

Other publications of authors with the same name

Register allocation for hybrid register architecture in nonvolatile processors.Y. Wang, H. Jia, Y. Liu, Q. Li, C. Xue, and H. Yang. ISCAS, page 1050-1053. IEEE, (2014)An 8b 0.8kS/s configurable VCO-based ADC using oxide TFTs with Inkjet printing interconnection.W. Sun, Q. Zhao, F. Qiao, Y. Liu, H. Yang, X. Guo, L. Zhou, and L. Wang. ISCAS, page 1-4. IEEE, (2017)Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.Q. Zhao, Y. Liu, W. Sun, J. Zhao, H. Yao, X. Guo, and H. Yang. DAC, page 80:1-80:6. ACM, (2017)A hierarchical C2RTL framework for FIFO-connected stream applications.S. Li, Y. Liu, D. Zhang, X. He, P. Zhang, and H. Yang. ASP-DAC, page 133-138. IEEE, (2012)A 3us wake-up time nonvolatile processor based on ferroelectric flip-flops.Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M. Chiang, Y. Yan, B. Sai, and H. Yang. ESSCIRC, page 149-152. IEEE, (2012)Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor.M. Xie, M. Zhao, C. Pan, J. Hu, Y. Liu, and C. Xue. DAC, page 184:1-184:6. ACM, (2015)Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration.D. Zhang, Y. Liu, X. Sheng, J. Li, T. Wu, C. Xue, and H. Yang. DAC, page 126:1-126:6. ACM, (2015)DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays.H. Zhong, S. Cao, L. Jiang, X. An, V. Narayanan, Y. Liu, H. Yang, and X. Li. IEEE Trans. Very Large Scale Integr. Syst., 29 (11): 1981-1993 (2021)STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS.Z. Yuan, Y. Liu, J. Yue, Y. Yang, J. Wang, X. Feng, J. Zhao, X. Li, and H. Yang. IEEE J. Solid State Circuits, 55 (2): 465-477 (2020)GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.G. Dai, T. Huang, Y. Chi, J. Zhao, G. Sun, Y. Liu, Y. Wang, Y. Xie, and H. Yang. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (4): 640-653 (2019)

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Disambiguation of "Liu, Yongpan"

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A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Dongmei Liu

Yinghao Liu

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Liu, Yongpan"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.

Please choose a person to relate this publication to

Liu Liu

Liu Liu

Liu Liu

Dongmei Liu

Yinghao Liu

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture.