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24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.

, , , , , , , , , , , и . ISQED, стр. 586-591. IEEE, (2012)

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Koji Kameo

Koji Onoda

Koji Ota

Tomoko Kojima

Hajime Kojima

 

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Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique., , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 21 (6): 1175-1179 (2013)Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor., , , , , , , , , и 4 other автор(ы). IEEE J. Solid State Circuits, 41 (8): 1692-1706 (2006)Session 18 overview: Adaptive circuits and digital regulators: Digital circuit techniques subcommittee., , и . ISSCC, стр. 298-299. IEEE, (2018)Misleading energy and performance claims in sub/near threshold digital systems., , , , , , , , , и 1 other автор(ы). ICCAD, стр. 625-631. IEEE, (2010)Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI., , , , , , , , , и 19 other автор(ы). IBM J. Res. Dev., 51 (5): 529-544 (2007)The circuit design of the synergistic processor element of a CELL processor., , , , , , , , , и 3 other автор(ы). ICCAD, стр. 111-117. IEEE Computer Society, (2005)24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits., , , , , , , , , и 2 other автор(ы). ISQED, стр. 586-591. IEEE, (2012)13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO., , , , , , , и . ISSCC, стр. 486-488. IEEE, (2012)Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS., , , , , , и . ISLPED, стр. 21-26. IEEE/ACM, (2011)12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics., , , , , , и . ISLPED, стр. 163-168. IEEE/ACM, (2011)